Single wafer integration, wherein all the components of a device are formed simultaneously on one wafer, has been a standard and successful practice in the semiconductor industry for decades. In the emerging fields of micromechanics and microsystems, however, advanced designs increasingly require a multiple wafer integration strategy, where the various components of a device are fabricated onto a plurality of wafers and then the processed wafers are bonded together to form the final product. The design situations that necessitate multiple wafer integration include complicated three-dimensional geometries, incompatibilities among fabrication processes and, particularly, the need to build device components on a wide palette of non-silicon starting wafer material types.
A number of bonding techniques are known that can produce strong, reliable bonds between wafers. Fusion bonding is a direct bonding process where two clean, flat surfaces, such as silicon, silicon dioxide, or silicon nitride, are covalently bonded through the application of pressure and heat. In anodic bonding a silicon surface and a borosilicate glass surface are fused through the application of strong electric fields and heat. Adhesive bonding is applicable to the widest range of wafer materials, but the bond strengths achieved are typically lower than those for either fusion or anodic bonding. Independent of the bonding method used, the first step in wafer bonding is to position the wafers in fixed relation.
There are applications where wafer bonding is performed without a precise alignment of the wafers to be bonded. If at least one of the wafers contains no device features then only a very coarse alignment may be necessary. This is the case for high purity silicon on insulator (SOI), where a bare silicon wafer is fusion bonded to a silicon dioxide-coated silicon wafer, and also when a bare wafer is bonded to a device wafer to serve as a cap or seal. In general, however, wafer bonding requires the initial steps of accurately aligning the components of a first wafer with the components of a second wafer and then holding the wafers in fixed relation for the bonding process.
Current methods for aligning wafers prior to bonding are time-consuming and require expensive equipment. In U.S. Pat. No. 5,236,118, entitled, "Aligned Wafer Bonding" by Bower et al. describes a wafer bonding process which uses a wafer aligned with precision mechanical stages and a sophisticated imaging system to optically align the wafers. The Bower et al patent teaches the use of infrared viewing to facilitate alignment of wafers. Wafer aligners based on infrared or alternative optical techniques are offered commercially by several semiconductor equipment manufacturers. They compare in complexity and price to lithographic contact aligners and require a similarly high level of skill to operate. For high volume manufacturing of wafer bonded devices, it would be advantageous to have a wafer bonding process with a low-cost wafer alignment step that did not require expensive capital equipment and could be performed quickly by unskilled operators or robotic assemblers. The use of commercial wafer aligners is currently restricted to the alignment of two wafers at one time. It would be a further advantage then to have a wafer alignment process that, in addition to the aforementioned benefits, could align three or more wafers for simultaneous bonding.